This invention relates to data processing apparatus. More specifically, the invention is concerned with data processing apparatus comprising a plurality of units interconnected by a bus, such that any unit can send a message over the bus to all the other units in parallel.
In such apparatus, it may be desirable to check that all the units correctly receive the message from the bus. One way of achieving this would be to arrange for each unit which receives the message to send an acknowledgement back over the bus to the sending unit. However, this could take an excessively long time, since it requires a separate bus cycle for each receiving unit to send its acknowledgement. Alternatively, each of the units could be provided with a separate acknowledgement line to each other unit, allowing all the receiving units to send their acknowledgements simultaneously to the sending unit. However, this requires a large number of special terminals on the units, which is undesirable, especially if each unit is implemented as a very-large scale integrated circuit (VLSI) chip, in which case the number of available terminals is limited.
The object of the present invention is therefore to provide an alternative way of checking that the message is correctly received, which does not suffer from these problems.